(In a nasal, Andy-Rooneyish tone) “Have you ever noticed how some things just stay new?”
Well, Prof. Jones’ paper is like that. It seems that every time I look at the paper, I see something new. Take for instance figure 2, the block diagram: I have been going over that paper on-and-off for a few years. Even so, I came up with the block diagram that I posted earlier. Hmmm, it seems that when I took another look at figure 2, I just tried fitting some 74LS00 series chips in place; what do you know? They fit! I looked at the buffer (the triangle pointing up, on the right side of the diagram) and thought that it could be a simple tri-state buffer; perhaps a couple/few 74LS241 Octal 3-State Drivers?
Next, I looked to the left a bit and noticed that the rectangle right next to the driver was really a latch, such as the 74LS373 or ‘374 (now what is the difference between those again? Oh yeah, one is edge triggered and the other is level triggered.) Whoa, those latches in Prof. Jones’ figure 2 look mighty close to these chips. In fact, with the exception of the triggers being inverted from Prof. Jones’ design, and the fact that the address latch is not buffered (just keep the output enabled for that one), those chips will work admirably.
After looking through my old, handy-dandy 7400 TTL list (http://en.wikipedia.org/wiki/List_of_7400_series_integrated_circuits), and doing a couple more replacements, I came up with this:
Notice that, as I’ve mentioned, the PC, ADDR and TEMP latches are inverted from Prof. Jones’ description. This can be easily handled by simply inverting the bits in the sequencer for those signals.
Also, the address decoding for the PC Register is the small box in the lower-left corner. It is simply a large AND gate looking for all the address bits to be high (the highest address) along with the write signal high. This will latch the data on the data bus into the 74LS374 holding the PC Register.
The sequencer will be a simple 74LS188 ROM (or actually half of one) programmed with the data from figure 3 in Prof. Jones’ paper. The address lines for this ROM will be tied to a 4-bit binary up counter (such as a 74LS161) clocked by the system clock. The eight bits per address location will line up with the eight signals coming in on the left-side of figure 2.
Next up will be creating a schematic of each part of figure 2, and the 74LS188 ROM with the counter and clock. I would like the clock to be variable, including down to single step, so that the operator can see each step as it is executed.
Also, January is the Winter Warmup for the Retrochallenge contest. I will be entering again (didn’t do as well as I would have liked last summer), but am not sure what I will be doing for that. Check out my RC blog at http://retrochallenge.granzeier.com (no longer valid.)
Additionally, I recently purchased a few of the LaunchPads from Texas Instruments. We will be going through an introduction to them in the next few weeks.